In recent years, high integration of semiconductor devices has been prompted. However, when a plurality of highly integrated semiconductor devices is arranged on a horizontal plane and is connected by wiring into a product, the length of the wiring may increase the resistance and make the delay of the wiring large.
Accordingly, the use of a three dimensional integration technology has been proposed which integrates semiconductor devices in three dimensions. In the three dimensional integration technology, for example, a joining system is used to join two semiconductor wafers (hereinafter, referred to as “wafers”) together. For example, the joining system includes a surface hydrophilization device which hydrophilizes the joining surfaces of wafers and a joining device which joins the wafers whose surfaces are hydrophilized by the surface hydrophilization device. In this joining system, the surface hydrophilization device hydrophilizes the surfaces of the wafers by supplying pure water to the surfaces of the wafers. Thereafter, two wafers are disposed in the joining device in a vertically opposing relationship (hereinafter, a wafer positioned at an upper side is referred to as an “upper wafer” and a wafer positioned at a lower side is referred to as a “lower wafer”). The upper wafer drawn and held by an upper chuck and the lower wafer drawn and held by a lower chuck are joined together by the Van der Waals force and by a hydrogen bond (an intermolecular force).
The lower chuck has, e.g., a flat plate shape, and draws and holds the lower wafer on the entire upper surface thereof. However, it is often the case that, due to the existence of irregularities on the upper surface of the lower chuck or the existence of particles or the like on the upper surface of the lower chuck, the upper surface of the lower chuck becomes uneven (or has a large flatness). In this case, the flatness of the lower chuck is transferred to the lower wafer. If the lower wafer and the upper wafer are joined together, a vertical distortion is generated in the joined superposed wafer.
In order to make the upper surface of the lower chuck flat, the upper surface of the lower chuck is sometimes subjected to, e.g., lapping, mirror treatment or the like. However, if the flatness of the upper surface of the lower chuck grows exceedingly smaller, thereby making the surface texture too fine, the lower wafer is hardly separated from the lower chuck when the vacuum suction of the lower wafer is released.